1. Field of the Invention
The present invention relates to a signal processing apparatus and an imaging apparatus. More particularly, the invention relates to processing and outputting a signal having a timing which is asynchronous with respect to input timing.
2. Description of the Related Art
In accordance with recent diffusion of personal computers, so-called digital cameras in which an image is recorded in a memory in the form of a digital signal are attracting notice as image input means for personal computers.
In digital cameras of this type, in general, an image signal obtained from a CCD (charge-coupled device), serving as an image pickup device, is converted into a digital signal, which is recorded in a memory by compressing the amount of digital information. Some digital cameras have the function of reproducing the recorded image signal and outputting the reproduced image signal to an external TV monitor, as well as the function of allowing confirmation of the currently photographed image on an incorporated monitor.
Recently, the tendency to provide digital cameras having higher-picture quality has accelerated. For that purpose, CCDs having a very large number of pixels are being used.
When the number of pixels of a CCD is increased in order to provide higher picture quality, a significant amount of time is required for reading an image signal from the CCD. In order to solve this problem, the clock frequency for driving the CCD may be increased. However, as the clock frequency increases, circuit elements, such as the CCD, an A/D (analog-to-digital) converter and the like, become more expensive.
Furthermore, when a significant amount of time is required for reading an image signal from the CCD, the frame rate, of a displayed image represented by the image signals decreases when displaying the image on an external monitor or an EVF (electronic view finder).
Hence, conventionally, when displaying an image on an external monitor or an EVF, the frame rate of the displayed image is increased by systematically reducing pixels of an image signal from the CCD, a simple integer ratio is provided between the frame rate of the image signal from the CCD and the frame rate of a display image signal, and the photographing system and the output system for the display image signal are driven in a synchronized state using the same timing signal in order to reduce circuit scale and simplify design.
FIG. 4 is a timing chart illustrating an example when driving the photographing system and the output system for display of the image signal in a synchronized state in the above-described manner. In the case of FIG. 4, the ratio of the frame rate of the image signal from the CCD to the frame rate of the display image signal is set to 1:2.
However, when circuitry is designed in order to satisfy the above-described condition, it is necessary to redesign the circuitry each time the number of pixels of the CCD changes because the synchronous timing of the image signal used in the photographing system and the synchronous timing of the image signal used in the external output system change.
In order to solve this problem, the photographing system and the external output system may be asynchronously driven. In such a case, however, a buffer storage having a very large capacity is required in consideration of changes in the timing between the photographing system and the external output system.
It is an object of the present invention to solve the above-described problems.
It is another object of the present invention to allow output of a signal at a timing which is asynchronous with input timing, with a simple configuration and without increasing circuit scale.
According to one aspect, the present invention which achieves these objectives relates to a signal processing apparatus including input means, first generation means for generating a first timing signal, reduction means for reducing a number of pixels of an input image signal using the first timing signal, a buffer memory for storing an image signal output from the reduction means, second generation means for generating a second timing signal which is asynchronous with the first timing signal, an image memory, and memory control means for writing the image signal stored in the buffer memory into the image memory in accordance with the first timing signal, and for reading the image signal stored in the image memory in accordance with the second timing signal.
According to another aspect, the present invention which achieves these objectives relates to an imaging apparatus including image pickup means for generating an image signal using a first timing signal, reduction means for reducing a number of pixels of the image signal obtained by the image pickup means, a buffer memory for storing an image signal output from the reduction means, an image memory, and memory control means for writing the image signal stored in the buffer memory into the image memory by performing burst transfer in accordance with the first timing signal, and for reading the image signal stored in the image memory in accordance with a second timing signal which is asynchronous with the first timing signal.
The foregoing and other objects, advantages and features of the present invention will become more apparent from the following detailed description of the preferred embodiment taken in conjunction with the accompanying drawings.